The High PHY IP is implemented on the ZU21DR Xilinx RFSoC, leveraging its superior processing power and RF capabilities.
Our IP interfaces seamlessly with the host server via PCIe QDMA in the ZU19EG Xilinx MPSoC (Multiprocessor System-on-Chip) of the Xilinx T1 card, ensuring efficient data transfer and communication.
The IP establishes a connection with the Remote Unit (RU) using 10/25G Ethernet in the MPSoC, enabling high-speed and reliable data transmission.
FAPI (Fronthaul Application Platform Interface) packets received from the MAC (Media Access Control) layer are efficiently forwarded to the RFSoC through the Aurora 64b/66b interface, optimizing data flow and processing.
The RFSoC performs robust high-level physical layer processing for each physical channel and reference signal. This includes channel encoding, modulation, resource element mapping, and reference sequence generation.
In the uplink path, the High PHY processing encompasses channel estimation and equalization, resource element demapping, demodulation, HARQ management and channel decoding, ensuring optimal performance and signal recovery.
The Processing System within the RFSoC handles complex mathematical computations on TTI (Transmission Time Interval) message parameters, ensuring accurate and efficient processing.
The High PHY data is forwarded to the MPSoC via the Aurora interface for fronthaul packing, enabling seamless integration with fronthaul protocols.
Our flexible hardware implementations enable scalable and cost-effective solutions.
Benefit from end-to-end support, spanning from software to hardware expertise.
Enjoy a scalable architecture with multiple options to meet evolving demands.
Experience interface simplicity, transport bandwidth scalability, interoperability, and function symmetry.
Transform your off-the-shelf hardware into powerful 5G processing units.