Our repeaters are optimized for Xilinx MPSoC, ensuring high-performance and reliability.
Seamless communication between FPGA and processor is achieved through PCIe data transfer, ensuring efficient data exchange.
The baseband data is received from the RF transceiver via the JESD204B interface
Two frame time domain data is buffered in DDR connected to the processing system (PS), providing efficient data storage and retrieval.
PSS (Primary Synchronization Signal) and SSS (Secondary Synchronization Signal) correlation are performed to detect symbol boundaries and calculate NCellID.
NCellID information is used for PBCH (Physical Broadcast Channel) decoding, enabling the determination of the radio frame boundary.
Based on the UL-DL (Uplink-Downlink) configuration, PDCCH (Physical Downlink Control Channel) and PDSCH (Physical Downlink Shared Channel) decoding can be performed in the PS.
SIB1 (System Information Block 1) is decoded using ASN1 decoding, allowing extraction of UL-DL configuration and PLMN ID.
The UL-DL configuration can be used to generate TSYNC in the programmable logic (PL) for TDD synchronization.
Our flexible hardware implementations enable scalable and cost-effective solutions.
Benefit from end-to-end support, spanning from software to hardware expertise.
Enjoy a scalable architecture with multiple options to meet evolving demands.
Experience interface simplicity, transport bandwidth scalability, interoperability, and function symmetry.
Transform your off-the-shelf hardware into powerful 5G processing units.